`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/16 09:06:11
// Design Name: 
// Module Name: eliminate_shake
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module eliminate_shake(
    input clk_200hz,
    input d_i,
    output d_o
    );
    
    wire clk_200hz_n = ~clk_200hz;
    reg [7:0] cnt = 8'b0;
    reg d_pos, d_neg;
    wire d_xor = d_pos^d_neg;
    
    always @(posedge clk_200hz) begin
        d_pos <= d_i;
    end
    always @(posedge clk_200hz_n) begin
        d_neg <= d_i;
    end
    
    always @(d_xor) begin        
    end
endmodule
